## Symbol timing recovery

The discussion in Chapter 3 on pulse shaping for minimum intersymbol interference highlighted the need for accurate timing of the sampling point within each symbol. A common symbol timing circuit is the early-late gate synchronizer. This circuit works on the basis that the optimum point to sample the signal at the output of a matched filter detector is when the signal is at its maximum.

The early-late gate approach uses two such detectors, one fed with a slightly advanced timing reference and one fed with a slightly retarded timing reference. The outputs of the two detectors are then periodically compared to see which is the larger. The timing is then advanced in favour of the detector with the larger output in the expectation that it will get bigger. Eventually, the timing will be advanced too far and the detector output begins to fall. The equilibrium point occurs when both detector outputs are equal (one falling away from the peak and one rising towards it), and the optimum sampling point is then known to lie midway between the advanced and retarded references. This optimum timing signal is passed to a third data detector. Two excellent references on timing and carrier recovery circuits are Lindsey (1972) and Gardner (1966). |